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lab3
- VHDL Lab 3 – Arithmetic & State Machines In this lab we will look at arithmetic circuits that add, subtract, and multiply numbers. Each type of circuit will be implemented in two ways: first by writing VHDL code that describes the require
VHDLbasic_cal
- VHDL的加、减、乘、比较等基本运算的源代码-VHDL add, subtract, multiply, compare the source code of the basic operations
LIA
- 该vhdl代码用两个rom模拟产生两路正弦波,并设计了一个乘法器将两路正弦波相乘。-The two vhdl code with two rom analog sine wave and design a multiplier to multiply two sine wave.
FinalCPU
- 用VHDL语言编写的简单CPU程序,实现了加减乘除和移位功能。-a simple CPU program writen by VHDL language , it realizes the add, subtract, multiply ,divide and shift function.
project
- 采用底层设计懂得乘法累加器一般设计方法,对于VHDL相关应用有一定帮助-Know how to multiply-accumulator general design method, the underlying design VHDL related applications
mac21
- this file is a multiply and accumulate logic built in VHDL platform.-this file is a multiply and accumulate logic built in VHDL platform.
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
cpu
- 基于VHDL的简易CPU设计,可以实现加、减、乘三种运算,模拟CPU的运算过程通过指令实现运算-Simple CPU design based on VHDL, three operation can realize add, subtract, multiply, simulation of the CPU operation process operation was achieved by instruction
EDA
- 采用一种基于FPGA的IIR数字滤波器的设计方案,通过QuartusⅡ的设计平台,采用自顶向下的模块化设计思想将整个IIR数字滤波器分为:时序控制、延时、补码乘加和累加四个功能模块。分别对各模块采用VHDL进行描述后,进行了仿真和综合。-IIR digital filter using a FPGA-based design, analyzes the theory and design method of IIR digital filter, then through QuartusⅡ de
my_multiplier
- 一个VHDL编的简单乘法器,基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, ser
calculate
- 基于VHDL,通过拨码开关实现数字输入,通过6位数码管实现输出。实现计算器的简单加、减、乘、除的基本功能-Based on VHDL, by DIP switch digital inputs, 6 digital control to achieve through output. Achieve a simple calculator to add, subtract, multiply, in addition to the basic functions
AnJian_1602
- 计算器设计。采用了现场可编程逻辑器件FPGA设计,并基于VHDL语言实现加减乘除功能,并用十进制显示在数码管上。计算部分为加法器、减法器、乘法器和除法器组成。使用Altera公司的QuartusII开发软件进行功能仿真并给出仿真波形,并下载到试验箱,用实验箱上的按键开关模拟输入,用数码管显示十进制计算结果。通过外部按键可以完成四位二进制数的加、减、乘、除四种运算功能,其结果简单,易于实现。-Calculator design. Using a field programmable logic d
bord-bord---Copy
- Total 32-bit floating-point and 32-bit floating-point multiply by VHDL language programming